DARPA kicks off $1.5B computer power tech research program

The Defense Advanced Research Projects Agency picks several teams in the industry and academic sectors for a five-year, $1.5 billion computer power technology research initiative.

The Defense Advanced Research Projects Agency has chosen several teams in the industry and academic sectors to participate in a five-year, $1.5 billion computer power technology research initiative.

DARPA started the Electronics Resurgence Initiative to explore new ways of developing flexible architectures and new chip designs that can use specialized hardware to power computers more effectively, the agency said Tuesday.

Industry participants for the ERI program include Northrop Grumman, Cadence Systems, Intel, Nvidia, Qualcomm, Systems & Technology Research, IBM, Skywater Technology Foundry, HRL Laboratories, Applied Materials, Xilinx and Synopsys. More than a dozen universities were chosen also.

They will work with DARPA to identify new materials, circuit design tools and systems architectures that can help increase the performance of microelectronics technology.

Launched in September of last year, the ERI initiative is divided into six so-called "Page 3" programs that derive that name to the economic and technology trend that later became known as Moore's Law.

Gordon Moore, an Intel co-founder, observed in a 1965 research paper that the number of transistors on a chip doubles every year while the costs get halved. DARPA says the Moore's Law concept is showing signs of slowing down as "it has become increasingly more challenging to ahieve performance gains from generalized hardware."

This is "setting the stage for a resurgence in specialized architectures," according to DARPA.

The six individual ERI programs and goals are as follows:

  • Intelligent Design of Electronic Assets: to produce a layout generator that helps users design electronic hardware within a 24-hour period.
  • Posh Open Source Hardware: to create an open source system for the design and verification of ultra-complex system-on-chip platforms.
  • Software-Defined Hardware: to develop hardware and software that can be reconfigured in real-time based on the data being processed, plus adapt the computing architecture for the workload and data at hand.
  • Domain-specific System on Chip: to develop a method for determining the right amount and type of hardware specialization while making a system as programmable and flexible as possible.
  • Three Dimensional Monolithic System-on-a-Chip: to develop materials, design tools and fabrication techniques for building microsystems on a single surface with a third dimension.
  • Foundations Required for Novel Compute: design circuits that leverage the properties of new materials and integration schemes to process data in ways that eliminate or minimize data movement.